Mobile electronic communication devices—including cellular telephones, pagers, smartphones, remote monitoring and reporting devices, and the like—have dramatically proliferated with the advance of the state of the art in wireless communication networks. Many such devices are powered by one or more batteries, which provide a Direct Current (DC) voltage. One challenge to powering electronic communication devices from batteries is that the battery does not output a stable DC voltage over its useful life (or discharge cycle) but rather the DC voltage decreases until the battery is replaced or recharged. Also, many electronic communication devices include circuits that operate at different voltages. For example, the Radio Frequency (RF) circuits of a device may require power supplied at a different DC voltage than digital processing circuits.
A DC-DC converter is an electrical circuit typically employed to convert an unpredictable battery voltage to one or more continuous, regulated, predetermined DC voltage levels, and thus to provide stable operating power to electronic circuits. Numerous types of DC-DC converters are known in the art. The term “buck” converter is used to describe a DC-DC converter that outputs a lower voltage than the DC source (such as a battery); a “boost” converter, also called a step-up, is one that outputs a higher voltage than its DC input.
Supplying power to an RF power amplifier of an electronic communication device is particularly challenging. The efficiency of an RF power amplifier varies with the RF signal amplitude. Maximum efficiency is achieved at full power, and drops rapidly as the RF signal amplitude decreases, due to transistor losses accounting for a higher percentage of the total power consumed. The loss of efficiency may be compensated by a technique known as “envelope tracking,” in which the output of a DC-DC converter, and hence the voltage supplied to the power amplifier, is not constant, but is modulated to follow the amplitude modulation of the RF signal. In this manner, at any given moment, the power supplied to the RF power amplifier depends on the amplitude of the signal being amplified.
FIG. 1 depicts the relevant RF output portion of an electronic communication device 10. A battery 12 provides a battery voltage VBAT to an efficient, wide-bandwidth envelope-tracking power supply 14 that modulates the supply voltage of the RF power amplifier (PA) 16. The RF PA 16 outputs an amplified RF signal for transmission from the device 10 on one or more antenna 18. The modulated voltage VPA(t) output by the dynamic power supply 14 should be capable of tracking a rapidly varying reference voltage. As such, the power supply 14 must meet certain bandwidth specifications. The required bandwidth depends on the specifications of the network(s) in which the RF PA 16 is used. For example, the required bandwidth exceeds 1 MHz for EDGE systems (8PSK modulation), and exceeds 30 MHz for LTE20 (Long Term Evolution).
A typical waveform of the RF envelope that must be tracked is shown in FIG. 2. This modulated voltage signal has a peak value VPA—max that can be higher than the battery voltage VBAT and an average value VPA—avg that also can be higher than VBAT depending on the PA 16 load-line optimization. The dynamic range of the signal is limited. The minimum value VPA—min is clamped (roughly at 1V) by a particular pre-distortion algorithm (referred to generically as ISO-Gain pre-distortion) that is used in envelope tracking operation in order minimize gain variations in the PA 16 linked to supply 14 modulation.
FIG. 3 depicts a block diagram of a parallel architecture 20 used in many envelope-tracking DC power supplies 14, in which a slow DC-DC converter 22 and a fast DC-DC converter 24 provide power to the RF PA 16 in parallel. The graph of FIG. 3 depicts the frequency response of the dynamic output of the slow and fast converters 22, 24—the slow converter 22 provides a higher power, but it is steady or only slowly varying; the fast converter 24 provides a lower power, but it rapidly changes over a wide range, to match the amplitude envelope of the RF signal. Parallel architectures such as this are normally used because the global efficiency can be much higher than in the case of series architectures (i.e., where a boost converter supplies a buck converter) where the total efficiency is the product of the efficiencies. Below is a mathematical analysis of the parallel architecture 20 of FIG. 3.
            P      OUT        =                  P        OUT_FAST            +              P        OUT_SLOW                        I      DC_FAST        =                  P        OUT_FAST                              η          FAST                ·                  V          BAT                                I      DC_SLOW        =                  P        OUT_SLOW                              η          SLOW                ·                  V          BAT                                η      TOT        =                            P          OUT_FAST                +                  P          OUT_SLOW                                      (                                                    P                OUT_FAST                                                              η                  FAST                                ·                                  V                  BAT                                                      +                                          P                OUT_SLOW                                                              η                  SLOW                                ·                                  V                  BAT                                                              )                ·                  V          BAT                          k    =                            P          OUT_FAST                          P          OUT_SLOW                    <      1      
From the last two equations can be derived an equation of the total efficiency of a parallel architecture, that is not the product of fast converter 24 efficiency and slow converter 22 efficiency.
      η    TOT    =            (              1        +        k            )        ·                            η          FAST                ·                  η          SLOW                                      k          ·                      η            FAST                          +                  η          SLOW                    
Total efficiency is also function of the ratio k=(POUT FAST/POUT SLOW ). FIGS. 4A and 4B show how, for a typical case where EffFAST=70% and EffSLOW=92%, the total efficiency varies with
  k  =                    P        OUT_FAST                    P        OUT_SLOW              .  
Several architectures have been developed in the prior art to meet the constraint of a DC-DC converter for envelope tracking. These can be divided in two groups: series architectures and parallel architectures.
In the series architecture, a relatively high voltage is required at the RF PA 16, such as 5V, but a battery may supply a VBAT of only 3.6V. Accordingly, a boost (step-up) DC-DC converter is connected in series with a buck (step-down) converter. FIG. 5 depicts a boost converter supplying a high switching frequency buck converter. FIG. 6 depicts a boost converter supplying a medium switching frequency, two-phase buck converter. In both cases, the efficiency is equal to the product of the boost converter efficiency and the buck converter efficiency—each of which is less than one, hence driving down the maximum total achievable efficiency.
Due to the efficiency limitations of the series architecture, a parallel architecture is better suited for envelope tracking operation. FIG. 7 depicts a slow buck DC-DC converter 22 in parallel with a fast linear regulator 24 to modulate power to an RF PA 16, as disclosed in U.S. Patent Application Publication No. 2005/064830. The slow buck converter 22 regulates the voltage at the VPA node by comparing it to a DC reference voltage (or, in some cases, a filtered version of the output of the linear regulator 24) to generate a feedback signal. The fast linear regulator 24 also regulates the voltage at the VPA node by comparing it to the modulated reference voltage obtained by tracking the amplitude envelope of the RF signal. Since there is no boost converter in this design, the maximum voltage available is VBAT supplied by the battery 12. Additionally, both the slow buck converter 22 and the fast linear regulator 24 attempt to regulate voltage at the same node. This creates a competition, with some current from the fast linear regulator 24 going to the slow buck converter 22 instead of to the load, and vice-versa. This current sharing has a very large deleterious effect on efficiency.
FIG. 8 depicts a parallel architecture in which a slow boost DC-DC converter 26 is added to the architecture of FIG. 7. This allows for voltages greater than VBAT from the battery 12. The slow boost converter 26 is loaded by the fast linear regulator 24. Similar to the series architecture, the efficiency of this arrangement is the product of the efficiency of the slow boost converter 26 and the efficiency of the parallel combination of the fast linear regulator 24 and the slow buck converter 22, which is necessarily lower than arrangement of FIG. 7, without the slow boost converter 26. Furthermore, the current sharing problem still exists, as both the slow buck converter 22 and fast linear regulator 24 attempt to regulate voltage at the same node.
FIG. 9 depicts a parallel architecture with a slow buck DC-DC converter 22 and fast linear regulator 24, and a link capacitor CFLY 28. This architecture is also disclosed in U.S. Patent Application Publication No. 2005/064830. The link capacitor 28 blocks DC current sharing between the slow buck converter 22 and the fast linear regulator 24. In this architecture, the fast linear regulator 24 regulates the node VPA—FAST, while the slow buck converter 22 regulates the node VPA. The addition of the fast and slow parts of the regulated power supply is imperfect, since the two regulators 22, 24 do not regulate the same node.
FIG. 10 depicts the parallel architecture of FIG. 9, with the addition of a low pass filter 30. The reference voltage for the slow buck DC-DC converter 22 is extracted from the output of the fast linear regulator 24, filtered by the low pass filter 30. The slow buck converter 22 in this architecture provides the average value of modulation.
FIG. 11A depicts a configuration taking the feedback for the fast linear regulator 24 at the regulated PA 16 node VPA. However, this configuration is inoperative because, due to the link capacitor 28, there is no DC continuity in the loop of the fast linear regulator 24. Accordingly, as depicted in FIG. 11B, a resistor 32 is placed in parallel with the link capacitor 28. This closes the DC loop for the fast linear regulator 24. However, the same problem now exists as discussed with reference to FIG. 7: current sharing between the slow buck DC-DC converter 22 and the fast linear regulator 24 degrades the efficiency of the system.
Another problem that is common to all of the parallel architectures discussed above is the reconfiguration of the system to operate in power level tracking mode rather than envelope tracking mode. When the RF PA 16 operates at low power, the envelope tracking does not provide any benefit in terms of efficiency. As a result, the RF PA 16 can be supplied with a DC voltage that is regulated as a function of the variation of the RF average power (rather than as a function of the instantaneous variations of the RF envelope), a slowly varying quantity.
All the presented solutions need a very low capacitance output capacitor COUT 69 connected to the VPA node in order to maximize the power efficiency of the converter 20 and to have large bandwidth. However, in power level tracking, this low capacitance is not able to filter the modulated current sunk by the PA 16 (which can be viewed as current sources sinking a variable current that varies as a function of the envelope of the RF signal). This leads to a very high voltage ripple on the VPA node, which is not suitable for RF applications.
For this reason, even in power level tracking mode, the architectures discussed above need to have the fast converter 24 operative in order to filter the ripple on VPA. In this configuration the reference of the fast converter 24 is at DC. Consequently, there is a degradation in efficiency due to the additional consumption of the fast regulator 24.
The Background section of this document is provided to place embodiments of the present invention in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.